1. Field of the Invention
This invention relates to a comparator circuit which is usable for the purpose of shaping and demodulating the waveform of data signal as detected in a receiver when it is attempting to demodulate data signal which is radiotransmitted from a transmitter in data communications.
2. Description of the Prior Art
In the case where data signal is transmitted from a radio transmitter of the type that the data signal is directly modulated through the use of a voltage-controlled oscillator incorporated in a PLL circuit, the data signal as detected in a receiver may tend to change in terms of DC voltage level used as reference, due to the frequency characteristics of demodulator of the transmitter and the characteristics of loop filter of the PLL circuit.
Furthermore, the data signal may include noise in an area of a weak electric field. It has conventionally been the practice that such data signal is used as output of a receiver by being waveform-shaped and demodulated by the use of a comparator circuit; with such practice, however, it often happens that error occurs in the data signal outputted from the receiver.
To provide a better understanding of the present invention, description is now given as to FIGS. 7 to 10 of the accompanying drawings.
FIG. 7 illustrates the voltage waveform of data signal having a varying DC voltage level which is obtained by detecting the waveform of data signal as transmitted, in a receiver, i.e., waveform of detection output. The detected data signal V.sub.IN changes in terms of the DC voltage level L1 that serves as a reference. Such data signal V.sub.IN is applied to a comparator circuit so as to be subjected to further waveform-shaping and demodulation. In FIG. 7 and the succeeding drawings, the abscissa represents time, and the ordinate indicates voltage level.
FIG. 8 is a circuit diagram illustrating a conventional comparator circuit. In comparator 23, detected data signal V.sub.IN applied to a terminal 21 is compared with a reference voltage V.sub.RE1 obtained by dividing power supply voltage V.sub.CC provided to a terminal 20, by means of resistors R20 and R21, so that when the data signal V.sub.IN goes above the reference voltage V.sub.RE1, the comparator provides a high-level output.
FIG. 9 shows waveforms which occur in the circuit of FIG. 8, and voltage waveform of data signal as transmitted from transmitter. More specifically, FIG. 9(A) represents the voltage waveform of the data signal V.sub.IN as detected together with the reference voltage V.sub.RE1 ; FIG. 9(B) shows the voltage waveform of output V.sub.0 of the comparator 23; and FIG. 9(C) indicates the voltage waveform of data signal V.sub.S as transmitted from transmitter.
Since the reference voltage V.sub.RE1 is fixed, the position of the cross-point between the data signal V.sub.IN and the reference voltage V.sub.RE1 (threshold voltage of the comparator 23) changes with time with respect to the data signal V.sub.IN.
The data signal V.sub.S as transmitted is of a perfect rectangular waveform, but when radio-transmitted, the data signal is restrained by adjacent channel leakage power so that it is modulated through a low pass filter in the transmitter. Thus, the data signal V.sub.IN resulting from the detection takes a pulse waveform wherein duty ratio changes at the rise and fall portions thereof, instead of such a perfect rectangular waveform as that of the data signal V.sub.S.
Thus, when the data signal V.sub.IN is compared with the reference voltage V.sub.RE1 at the center of the amplitude thereof, the waveform of the data signal V.sub.S as transmitted from the transmitter is obtained as output of the comparator 23 so that waveform shaping is effected satisfactorily. If the position of the reference voltage V.sub.RE1 is shifted upwardly and downwardly from the center due to variations in the DC voltage level of the data signal V.sub.IN, however, the waveform of the output V.sub.0 obtained from the comparator 23 turns out different in respect of duty ratio from the data signal V.sub.S transmitted from the transmitter.
A comparison of the output V.sub.0 and the data signal V.sub.S reveals that part 91 of the output V.sub.0 is narrower than the corresponding part 81 of the data signal V.sub.S. This is due to the fact that at the part 71 of the data signal V.sub.IN which corresponds to the part 81 of the data signal V.sub.S, comparison of the date signal V.sub.IN and the reference voltage V.sub.RE1 is effected at a position which is close to the low level and where the waveform becomes narrower.
Further, part 92 of the output waveform V.sub.0 is broader than corresponding part 82 of the data signal V.sub.S. This is due to the fact at that part 72 of the data signal V.sub.IN which corresponds to the part 82 of the data signal V.sub.S, comparison of the data signal V.sub.IN and reference voltage V.sub.RE1 is effected at a position which is close to the high level and where the waveform becomes broader.
Part 93 of the output waveform V.sub.0 also is broader than corresponding part 83 of the data signal V.sub.S. This is due to the fact that comparison of that part 73 of the data signal V.sub.IN which corresponding to the part 83 of the data signal V.sub.S and the reference voltage V.sub.RE1 is effected at a position which is close to the high level and where the waveform becomes broader.
The high level and low level of the data signal V.sub.IN represents bit information; thus, due to the difference from the data signal V.sub.S of the output V.sub.0 derived from the comparator the 23, bit error is caused to occur so that error signal which is not based on the data signal V.sub.IN is transmitted.
FIG. 10 is a circuit diagram showing another conventional comparator circuit. Detected data signal V.sub.IN applied to terminal 30 is passed to an integrating circuit consisting of a resistor R30 and capacitor C30, and comparison of the output of the integrating circuit used as the reference voltage V.sub.RE1, and the data signal V.sub.IN is effected in the comparator 32.
FIG. 11 illustrates the waveform of the data signal V.sub.IN in which DC voltage level L1 varies, and that of the reference voltage V.sub.RE1 in the circuit of FIG. 10. The reference voltage V.sub.RE1, varies with a variation in the DC voltage level L1. More specifically, the reference voltage V.sub.RE1 approaches the high level as persistency of the high level of the data signal V.sub.IN increases, while it approaches the low level as persistency of the low level of the data signal V.sub.IN increases. As a result, the reference voltage V.sub.RE1, occurs dominantly at the site where more contiguous-bit information occurs. The reference voltage V.sub.RE1 varies behind the bit information.
As will be seen from the above discussion, the conventional comparator circuits of FIGS. 8 and 10 is disadvantageous in that bit error is often caused to occur in the output of the comparator circuit due to the fact that the reference voltage V.sub.RE1 which is compared with the the data signal V.sub.IN is not located at the center of the amplitude of the data signal V.sub.IN.